AK4399 PDF

Quote: Unfortunately, the chip, while important, does not have as much to do with the sound as one might expect. The circuit design and the care in which it is implemented is more important. Thus there are wonderfully sounding units with 10 year old chip designs and with the latest chips. What he said. This seems to be a very popular trap to fall into for newbies and know-it-alls alike.

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An internal circuit includes newly developed 32bit Digital Filter for better sound quality achieving low distortion characteristics and wide dynamic range. The AK has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. Sampling Rate: 30kHz? High Tolerance to Clock Jitter? Low Distortion Differential Output? DSD data input? Digital De-emphasis for 32, Soft Mute? Digital Attenuator levels and 0. Mono Mode?

External Digital Filter Mode? Power Supply: 4. The AK should always be reset upon power-up. I Connect to GND. No internal bonding. These pins must be open. This pin must be connected to VSS4. This pin must be open. These pins must be connected to VSS4. All voltages with respect to ground. Note 2. VSS must be connected to the same analog ground plane. Normal operation is not guaranteed at these extremes. Note 3. Note 4. AOUT typ. Measured by Audio Precision, System Two.

Averaging mode. Refer to the evaluation board manual. Note 6. Note 7. Note 8. Note 9. Full-scale voltage 0dB. Note DC load is 1.

The load resistance value is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected to the output pin.

Therefore the capacitive load must be minimized. In the power down mode. The passband and stopband frequencies scale with fs. The calculating delay time which occurred by digital filtering. DSD data transmitting device must meet this time. EXD bit controls the modes. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator.

Sampling speed and MCLK frequency are detected automatically and then the initial master clock is set to the appropriate frequency Table 3.

The frequency of DCLK is fixed to 64fs. Three formats are available Table 9 by DIF bits setting. The data is latched on the rising edge of BCK. These volume control is in front of the DAC and it can attenuate the input data from 0dB to —dB and mute.

When changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions. The zero detect function can be disabled by setting the DZFE bit.

This function is available for any audio format. If the soft mute is cancelled before attenuating? The soft mute is effective for changing the signal source without stopping the signal transmission. Figure It initializes register settings of the device. As some click noise occurs at the edge of the PDN pin signal, the analog output should be muted externally if the click noise influences system application.

As some click noise occurs at the edge of RSTN signal, the analog output should be muted externally if click noise aversely affect system performance. Figure 14 shows an example of reset by RSTN bit. The timing example is shown in this figure. In parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored. Internal registers may be written to through3-wire?

In serial control mode, the internal timing circuit is reset by the RSTN bit, but the registers are not initialized. All registers are not initialized. This digital attenuator is independent of soft mute function. Figure 19, Figure 20 and Figure 21 show the analog output circuit examples. The evaluation board AKD demonstrates the optimum layout, power supply arrangements and measurement results.

Ground Layout 1. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin. F ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency noise. Analog Outputs The analog outputs are full differential outputs and 2.

If the summing gain is 1, the output range is 5. The bias voltage of the external summing circuit is supplied externally. The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps. The AK can achieve this filter response by combination of the internal filter Table 16 and an external filter Figure Frequency Gain 20kHz?

As used here: Note1 A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2 A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.


AK4399 32bit Audio DAC PCB kit











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